Delay-Optimal Ordering of Wires in Interconnect Channels

The problem of ordering and sizing parallel wires residing in a single metal layer within an interconnect channel is addressed in this paper. Wires are ordered such that cross-capacitances between neighboring wires are optimally shared for circuit delay minimization. Using an Elmore delay model including cross capacitances, an optimal wire ordering is uniquely determined, such that average signal delay can be minimized by proper allocation of inter-wire spaces. For uniform-width wires, the optimal order depends on the size of drivers, and is independent of size of receivers. The optimal order corresponds to minimal differences between driver resistances of neighboring wires. This result applies to most practical VLSI design scenarios. The problem of simultaneously ordering and optimizing variablewidth wires is addressed also. The same ordering method is shown to be advantageous for minimizing the critical wire delay in most problem instances. Examples for 65-nanometer technology are analyzed and discussed.